Many integrated circuits (“ICs”) are made up of millions of interconnected devices, such as transistors, resistors, capacitors, and diodes, on a single chip of semiconductor substrate. Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
In some instances, a second IC is stacked on an IC (“stacked IC”). The first and second ICs are electrically connected, and the combination of the two ICs is packaged and used as a single component. The second IC could be a read-only memory, random access memory, a processor, or an application specific IC (ASIC), for example. The front side of the second IC is typically attached to the backside of the first IC, and the ICs are electrically connected to each other using solder bumps, backside pads, and through vias (i.e., vias that extend through the first IC to electrically connect a pad on the backside of the first IC with a pad or solder bump on the front side of the first IC). The first (parent) IC is designed to interface with the second (daughter), which might be a standard component or a component specifically designed to interface with the parent IC. Stacked ICs are singulated from the wafer as dice and electrically tested before being packaged, such as by using a flip-chip package technique.
Yield loss arising from the die stacking process often occurs. Testing stacked IC wafers avoids processing the failed stacked IC chips into packaged ICs Depending on the specification of die-stacking technology (via pitch, aspect ratio, density, etc.), we have less than 100% yield during stacking. So, we need to test the stacked-die interface before packaging. It is possible that the stacked die might need to be tested for speed. It is desirable to provide techniques for testing wafers having stacked ICs.